26 Mar Xilinx Everest: Enabling FPGA Acceleration With ACAP

Xilinx , the leading vendor for Field Programmable Gate Array (FPGA) chips, has announced its widely-expected 7nm generation architecture, called Everest, targeting datacenter acceleration applications as well as AI, IOT and the company’s traditional markets. While most market observers expected Xilinx to beat Intel (Altera) to the 7nm milestone, the scope of the Everest program and the focus on the Adaptable Computing Acceleration Platform (ACAP) is what sets the company apart. Xilinx has had several successes over the last 18 months in the datacenter, most notably with Amazon Web Services (which I have covered here and here).

What did Xilinx announce?

The scope of the Everest project is impressive: 1,500 engineers working for four years to build a chip with fifty billion transistors, with total costs running over $1B. To give you a feel for the size of this beast, the NVIDIA Volta GPU is perhaps the current chip champ, with twenty-one billion transistors; this XILINX reprogrammable chip is about 2.5 times as large. More importantly, the chip turns out 20 times the performance of the company’s existing FPGAs for AI applications. Xilinx also stated that the performance over a CPU ranges from 10X for image processing, to 90X for data analytics, to 100X for genomic sequencing. Xilinx has focused on these markets with the Amazon AWS Marketplace, partnering with IP providers NGCodec, Ryft, and Edico Genome.

ACAP: A new device category?

Beyond the speeds and feeds are technologies that Xilinx believes can enable a larger market of adopters to accelerate workloads: the Adaptable Computing Acceleration Platform, or ACAP. Xilinx began this journey with its Reconfigurable Acceleration Stack in late 2016, providing software and IP blocks to accelerate Machine Learning and other datacenter apps. The problem it was beginning to solve was reducing the barriers to adoption of FPGAs for accelerated compute-intensive datacenter workloads—considerable barriers given the combination of hardware and software expertise required.

Xilinx is now embedding new functions in Everest that will take this a step further. So much further that Xilinx is calling ACAP an entirely new device category. While that marketing may appear to be a bit hyperbolic, the benefits from these on-die functions could be dramatic. Specifically, an ACAP includes HW/SW programmable engines, Application and Real-Time Processors, and a slew of next-gen I/O blocks, all interconnected with an on-die network fabric. Exactly what these new engines and processors will support remains to be seen, but conceptually they should enable one to transfer current software and IP blocks for acceleration directly onto the Everest die, simplifying application development and significantly improving performance.

Figure 1: Xilinx contends that Everest will greatly simplify programming for FPGA acceleration in the datacenter and in IOT applications


Xilinx has developed significant expertise and a small but growing ecosystem for application acceleration in the data center and in the world of IoT. Transferring that expertise directly onto its next-generation chip could dramatically improve performance while lowering barriers to adoption. Clearly, companies including Amazon Web Services, Baidu , and Microsoft recognize that FPGAs provide reconfigurable acceleration hardware to speed critical applications such as AI, graphics encoding, genome analyses, fast networking, and complex queries. With ACAP, Xilinx now has the potential to take this concept to the next level, allowing FPGAs to cross the chasm to broad adoption in the next few years.