14 Nov Lattice Sampling CrossLinkPlus FPGAs For Embedded Vision Systems

CrossLinkPlus aggregates multiple sensors and pre-processes data to offload processor 
LATTICE

Lately I’ve been paying extra close attention to Lattice Semiconductor as I watch its rapidly improving focus and financials. In the past year, it installed respected AMD veteran Jim Anderson as CEO (along with a crack team of other FPGA industry veterans), and has really doubled down on its efforts to become the low power FPGA leader. If interested, I did a deep dive on the company’s transformation after attending the company’s Financial Analyst Day back in May which you can read here and read how I grade Anderson after a year here

Over the summer, Lattice followed up with some new offerings, including a new FPGA called MachXO3D, with built-in hardware-based security, and an upgrade of the company’s sensAI stack (see my take here). This week Lattice made news again during its earnings announcing it was sampling, “ahead of schedule”,  its new family of FPGAs, entitled CrossLinkPlus, geared towards MIPI D-PHY-based embedded vision systems. I then realized that I hadn’t yet weighed in on CrossLinkPlus.

What is CrossLinkPlus?

Lattice designed the CrossLinkPlus family of FPGAs to enable developers to add multiple image sensors and displays to embedded vision systems in manner that is low power and low cost. To achieve this, CrossLinkPlus includes a number of cutting-edge features. It boasts a pre-verified, hardened MIPI D-PHY interface, capable of supporting speeds up to 6 Gbps per port. Also it includes on-device, non-volatile reprogrammable flash memory, which according to Lattice allows for instant-on capabilities under 10 milliseconds and supports flexible device reprogramming in the field.

Before, a custom ASIC required for each display type, but now only one CrossLink required 
LATTICE

Additionally, Lattice touts CrossLinkPlus’s support for various high-speed I/O interfaces (including LVDS, SLVS, RGB, and subLVDS), its IP library (including MIPI CSI-2, MIPI DI, and Open LDI transmitters and receivers), and compatibility with Lattice’s Diamond design software tool flow. Also, in characteristic Lattice fashion, the CrossLinkPlus family boasts impressively efficient power consumption—as low as 300µW for standby and 5mW for operating. To top it all off, these features come in a tiny 3.5 x 3.5 mm package. 

The benefits of these features are increasingly important in embedded vision applications across a number of vectors—automotive, industrial, computing, consumer, and more. Lattice contends that this marriage of vision-specific hardware, software, IP, and reference designs with FPGAs will enable OEMs to spend more time innovating and less time on standard functions. And I agree.  

Wrapping up

All said, the new CrossLinkPlus family looks to be a healthy addition to Lattice Semiconductor’s impressive and growing portfolio of low power FPGA offerings. Embedded vision is a strategic growth area, and it makes sense that Lattice would target it. Lattice, under CEO Jim Anderson, appears to be firing on all cylinders towards its goal of becoming the low power FPGA industry leader. I’ll continue to watch with interest.